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| 1994,1996 data sheet mos integrated circuit m pd9930 linear codec for digital cellular telephone the m pd9930 is a +3 v single power operation, low power consumption linear codec lsi developed for digital cellular telephone use. codec has a wide dynamic use. this ic also features a microphone/receiver amplifier, a tone generator, dai (digital audio interface: conforming to gsm11.10), and a power-saving function. these functions can be controlled by microcontroller. in addition, 21 mw (typ.) low power consumption is enabled during 3 v operation. features ? +3 v single power supply ? low power consumption in operation: 7 ma (typ.) (v dd = 3 v) in stand-by mode: 50 m a (typ.) (v dd = 3 v) ? codec ? 13-bit precision linear coding ? transmission level can be controlled by microcontroller. ? analog input/output funciton ? low noise microphone amplifier ? high output receiver amplifier piezo-electric receiver can be directly driven. gain canbe controlled by microcontroller. ? on-chip amplifier for accessory input/output ? tone generator ? frequency, generating pattern and gain can be controlled by microcontroller. ? dtmf generation function ? various service tone generation function ? gsm triple tone generation function ? desired tone frequency can be registered (0.3 to 3.4 khz) document no. s11616ej2v0ds00 (2nd edition) (previous no. ic-3342) date published november 1996 n printed in japan the information in this document is subject to change without notice. ? dai ? conforming to gsm11.10 ? test mode can be set by terminal or microcontroller command. ? stand-by mode ? rise time at time of stand-by clearing: 30.5 ms (typ.) ? master clock generation pll (external clock input: 8 khz) ? tone interrupt pattern output function ? ringer output function ordering information part number package m pd9930g-22 44-pin plastic qfp (10 10 mm) the mark shows major revised points.
m pd9930 2 resetb reqb fsync sclk (256 khz) sen so si dspsel mclk mstr mdat dclk do di tc1 tc2 drstb dai (gsm11. 10) low-current drive led timer micro- controller interface dsp interface receive lpf voice send digital gain cont. 0 to ?.8 db (0.4 db steps) transmit bpf pll digital signal processor d/a a/d pre-filter + mixer 0 or ? db ringer v ref v combuff racomo racomi xacomi xacomo rec2o+ rec2o ref + + receiver drive amplifier (receiver amplifier 2) rec2i rec1o post filter 1 (accessory output amplifier) 0 db fix post filter 2 (receiver amplifier 1) 0 to -31 db (1 db steps) to v ref rauxo xauxi xauxo (to xacomo) mici+ mici mico mixi microphone amplifier + + sign code output (15 to 33 db) (0 to 10 db) to v ref to v voice receive digital gain cont. 0 to ?.4 db (0.8 db steps) tone gain cont. 0 to ?0 db (1 db steps) ?8.5 db tone generator tone interval generation (8 khz) accessory input amplifier block diagram m pd9930 3 1234567891011 33 32 31 30 29 28 27 26 25 24 23 34 35 36 37 38 39 40 41 42 43 44 22 21 20 19 18 17 16 15 14 13 12 rec1o rauxo av dd1 av dd2 dv dd sen si so sclk test mstr mico mici mici+ agnd4 agnd3 agnd2 agnd1 dgnd fsync resetb reqb rec2i ic note rec2o rec2o+ racomi racomo xacomo xacomi xauxi xauxo mixi mdat mclk drstb di do dclk tc1 tc2 timer ringer dspsel note internal connection; leave unconnected pin configuration (top view) 44-pin plastic qfp (10 x 10 mm) m pd9930 4 pin name agnd1-agnd4 : analog ground av dd1 , av dd2 : analog power supply dclk : dai (digital audio interface) clock output dgnd : digital ground di : dai serial input do : dai serial output drstb : dai reset dspsel : digital signal processor select dv dd : digital power supply fsync : frame synchronization signal input ic : internally connected mclk : microcontroller synchronous clock mdat : microcontroller serial data mici+ : microphone amplifier input non-inverted miciC : microphone amplifier input inverted mico : microphone amplifier output mixi : mixer input mstr : microcontroller strobe racomi : receive common reference voltage input racomo : receive common reference voltage output rauxo : receive auxiliary amplifier output rec1o : receive amplifier 1 output rec2iC : receive amplifier 2 input inverted rec2o+ : receive amplifier 2 output non-inverted rec2oC : receive amplifier 2 output inverted reqb : request resetb : reset ringer : ringer sclk : serial data synchronous clock output sen : serial data output enable si : serial data input so : serial data output tc1, tc2 : dai mode control test : test timer : timer xacomi : transmit common reference voltage input xacomo : transmit common reference voltage output xauxiC : transmit auxiliary amplifier input inverted xauxo : transmit auxiliary amplifier output m pd9930 5 contents 1. pin functions ........................................................................................................................... 6 1.1 list of pin functions ..................................................................................................................... 6 1.2 pin equivalent circuit .................................................................................................................. 8 2. block functions ..................................................................................................................... 9 2.1 codec ............................................................................................................................... ..................... 9 2.1.1 audio codec .............................................................................................................................. 9 2.1.2 audio analog input .................................................................................................................. 9 2.1.3 audio analog output ............................................................................................................. 10 2.1.4 audio digital accessory output ........................................................................................... 11 2.1.5 audio digital signal processor ............................................................................................ 11 2.1.6 power up/down control ........................................................................................................ 12 2.1.7 microcontroller interface ....................................................................................................... 18 2.1.8 dsp interface .......................................................................................................................... 19 2.1.9 dai (digital audio interface) ................................................................................................. 22 3. tone interval output function (timer terminal) ................................................. 29 4. internal control functions ...........................................................................................30 4.1 send/receive gain control ...................................................................................................... 30 4.1.1 voice send analog gain/receiver amplifier 2 control register (txgcr) .................... 32 4.1.2 voice receive analog gain control register (rxgcr) ................................................... 33 4.1.3 voice send/receive digital gain control register (dggsr) .......................................... 35 4.2 digital input/output control ................................................................................................. 37 4.2.1 digital signal processing control register (dspcr) ....................................................... 38 4.3 tone control ............................................................................................................................... ... 40 4.3.1 tone frequency selection register (frqsr) .................................................................... 43 4.3.2 expanded tone registers (expr1, expr2) ....................................................................... 45 4.3.3 tone control register (toncr) ........................................................................................... 47 4.3.4 tone gain control register (tngcr) ................................................................................. 48 4.4 test mode control ...................................................................................................................... 50 4.4.1 test control register (tstcr) ............................................................................................. 52 5. electrical characteristics ............................................................................................53 6. applied circuit example .................................................................................................... 73 7. package drawings ............................................................................................................... 74 8. recommended soldering conditions ......................................................................... 75 m pd9930 6 tc2 tc1 test mode specification l l normal operation l h speech encoder test mode h l speech decoder test mode h h acoustic device test mode 1. pin functions 1.1 list of pin functions table 1-1 list of pin functions (1/2) pin no. pin name input/output function 1 mdat input microcontroller interface serial input 2 mclk input microcontroller interface clock input 3 drstb input dai (digital audio interface) reset input this is reset at low level. internally pulled high. 4 di input dai serial input internally pulled high. 5 do output dai serial output hi-z in normal operation (tc1 = tc2 = low level) 6 dclk output dai clock output (104 khz) hi-z in normal operation 7 tc1 input 8 tc2 input 9 timer output timer output. output of rectangular wave synchronized with tone intermittent pattern. 10 ringer output ringer tone output. output of rectangular wave synchronized with tone fre- quency. 11 dspsel input selection of dsp interface input/output timing mode. connect to v dd or gnd. (v dd = mode 1, gnd = mode 2) 12 reqb input input of dsp interface data transmit request signal. serial data can be input/output at low level. 13 resetb input system reset input. this is reset at low level. initializes all control registers. reset when turning power on. 14 fsync input send/receive frame synchronization signal (8 khz) input 15 dgnd digital ground. connect to a digital ground line near m pd9930 pins. 16 agnd1 analog ground. connect to an analog ground line near m pd9930 pins. 17 agnd2 18 agnd3 19 agnd4 20 mici+ input microphone amplifier non-inverted input 21 miciC input microphone amplifier inverted input 22 mico output microphone amplifier output. connect microphone amplifier gain adjust resistor. outputs sidetone signal to rec2i- pin. 23 mixi input pre-filter + mixer input 24 xauxo output accessory input amplifier output. connect accessory input amplifier gain adjust resistor. dai mode control selection of test mode specified by gsm11.10 in combination with tc1 and tc2 l: low level h: high level tc1 and tc2 pins are internally pulled down. m pd9930 7 table 1-1 list of pin functions (2/2) pin no. pin name input/output function 25 xauxiC input accessory input amplifier inverted input 26 xacomi input voice send internal reference voltage input 27 xacomo output voice send internal reference voltage (1.2 v) output 28 racomo output voice receive internal reference voltage (1.2 v) output 29 racomi input voice receive internal reference voltage input 30 rec2o+ output receiver amplifier 2 non-inverted output 31 rec2oC output receiver amplifier 2 inverted output 32 ic internal connection; leave unconnected 33 rec2iC input receiver amplifier 2 inverted input connect sidetone gain adjust resistor. 34 rec1o output receiver amplifier 1 output 35 rauxo output accessory output amplifier output 36 av dd1 analog power. connect to an analog power supply line near m pd9930 pins. 37 av dd2 38 dv dd digital power. connect to a digital power supply line near m pd9930 pins. 39 sen output dsp interface enable signal output 40 si input dsp interface serial input 41 so output dsp interface serial output 42 sclk output dsp interface clock output (256 khz) 43 test input set at high level 44 mstr input microcontroller interface strobe signal input caution short-circuit the xacomi and xacomo pins at a location as close to the pins of the m pd9930 as possible. connect a capacitor (chip capacitor or electrolytic capacitor) between this short-circuited portion and analog ground. the same applies to the racomi and racomo pins. the transmission/reception level is determined by these reference pins. therefore, make sure that these pins are not affected by noise or fluctuation of ground potential due to current. m pd9930 8 av dd analog input to internal circuit agnd av dd analog input to internal circuit agnd av dd analog output from internal circuit agnd dv dd cmos input to internal circuit dgnd dv dd cmos input to internal circuit dgnd dv dd cmos input to internal circuit dgnd mask input dv dd cmos input to internal circuit dgnd dv dd dgnd cmos output dv dd from internal circuit p n dgnd cmos output dv dd from internal circuit p n enable signal type 2 type 1 type 3 type 5 type 4 type 7 note type 6 note type 9 type 8 pin name mici+, mici? xauxi? rec2i pin name mico, xauxo, xacomo, racomo, rec2o+, rec2o? rec1o, rauxo pin name si pin name drstb, di pin name do, dclk pin name mixi, xacomi, racomi pin name mdat, mclk, dspsel, reqb, resetb, fsync, test, mstr pin name tc1, tc2 pin name timer, ringer, sen, so, sclk 1.2 pin equivalent circuit note in normal mode, set the output of drive ic side to high impedance for reducing power consumption. m pd9930 9 to v ref xauxi xauxo (0 to 10 db) (to xacomo) mici+ mici (15 to 33 db) mico mixi accessory input amplifier microphone amplifier + + r2 r1 r1 r3 r4 pre-filter + mixer 0 or ? db 2. block functions 2.1 codec 2.1.1 audio codec audio analog signal and linear code conversion. ? input/output format: 16 bits (2's complement) ? accuracy: 13 bits 2.1.2 audio analog input includes microphone input and accessory input. (1) microphone amplifier amplifiers differential input signals from the microphone to the required gain. (2) accessory input amplifier amplifiers the accessory input signal to the required gain. (3) pre-filter + mixer selects the output signal of microphone amplifier and accessory input amplifier, and inputs these to a/d converter after controlled gain. table 2-1 analog input function function gain setting method external resistor external resistor microcontroller command gain setting range 15 to 33 db 0 to 10 db 0 or C3 db 20 log (db) 20 log (db) minimum resistive load 50 k w 300 k w (including gain setting resistance) (including gain setting resistance) maximum capacitive load 20 pf 20 pf maximum output level 0.6 v 0-p 0.6 v 0-p figure 2-1 analog input block amplifier r2 r3 r1 r4 microphone amplifier accessory input amplifier pre-filter + mixer m pd9930 10 rec2o+ rec2o to v ref + + receiver drive amplifier (receiver amplifier 2) rec2i rec1o post filter 1 (accessory output amplifier) 0 db fix rauxo r2 r1 r3 sidetone signal to v ref post filter 2 (receive amplifier 1) 0 to ?1 db (1 db steps) r3 r2 r3 r1 2.1.3 audio analog output includes receiver output and accessory output. sidetone addition is also possible. (1) post filter 2 (receiver amplifier 1) this circuit adjusts the gain of d/a differential output signal (volume control), and then converts it to single output signal. (2) receiver drive amplifier (receiver amplifier 2) this is differential output amplifier that can directly drive a piezo-electric receiver (when using a dynamic receiver, an additional external amplifier is necessary). the sidetone is added in this circuit. (3) post filter 1 (accessory output amplifier) this circuit converts d/a differential output signal to single output signal. connected to the earphone of the head set (capacitance load), etc. table 2-2 analog output functions function gain setting method microcontroller command external resistor gain setting range 0 to C31 db (1 db steps) voice receive signal gain: C to + 10 db 20 log (db) + 6 db note sidetone signal gain: C to + 3 db 20 log (db) + 6 db note minimum resistive load 100 k w 2 k w 100 k w maximum capacitive load 20 pf 60 nf 100 pf maximum output level 0.6 v 0-p 4 v p-p (differential output) 0.6 v 0-p note conversion result (single output ? differential output) figure 2-2 analog output block amplifier receiver amplifier 1 receiver amplifier 2 accessory output amplifier m pd9930 11 timer ringer rec10 rauxo (tone output) ringer rauxo (tone output) 2.1.4 audio digital accessory output (1) ringer output (ringer pin) ? outputs rectangular waves of the same signal frequency as tone signal frequency. ? the output is controlled by turning off power to the output buffer with a control register. figure 2-3 ringer output the ringer signal tends to bounce when the tone output (rauxo) signal crosses its zero level, and this tendency increases as the tone output gain decreases (lower than 0 db). when using ringer pin, tune the tone output gain by tngcr (tone gain control register) to 0 db. (2) timer (tone interval) output (timer pin) outputs rectangular waves of the same pattern as the tone signal interrupt pattern. this is used to make the led blink in synchronization with the ringer tone. figure 2-4 digital accessory output waveform 2.1.5 audio digital signal processor send signal digital bpf processing, receive signal digital lpf processing, transmission level (digital gain) control, and tone generation processing. (1) voice send signal digital gain fine adjustment function performs gain fine adjustment for voice send signal by digital coefficient multiplication. together with prefilter gain adjustment, fine adjustment is possible at a width of 5.8 db. (2) voice receive signal digital gain fine adjustment function performs fine adjustment of gain for voice receive signal by digital coefficient multiplication. (3) tone generation function generates single-tone and dual-tone audible signals. tone frequency, interrupt pattern, gain, generation/stop can be controlled by microcontroller command. gsm triple tone can be generated by special command. m pd9930 12 table 2-3 digital gain control functions voice send signal gain control voice receive signal gain control tone gain control gain setting method microcontroller command microcontroller command microcontroller command gain setting range 0 to C2.8 db (0.4 db steps) 0 to C2.4 db (0.8 db steps) 0 to C30 db (1 db steps), C38.5 db 2.1.6 power up/down control the m pd9930 includes a power down function for reducing power consumption. power down control is by the two methods described below. (1) input/output amplifier power up/down control power up/down for both the input and output amplifiers can be controlled. when the power down function is used for all input amplifiers, both pre-filter and a/d enter the power down state. when the power down function is used for the accessory output amplifier and the receiver 1 amplifier, the d/a also enters power down state. (2) stand-by mode low power consumption can be realized in the mode in which all chip operation is stopped. the stand-by mode is set by power down command. operation restarts by power up command. the following control registers are used to enable the control described above. control method registers used power up/down control of input/output amplifier input/output amplifier control register (ampcr) (not including receiver amplifier 2) power up/down control of receiver amplifier 2 send analog gain/receiver amplifier 2 control register (txgcr) set/clear of standby mode power up control command (pupcmd) power down control command (pdwcmd) an outline diagram of power down control is shown in figure 2-5 . m pd9930 13 figure 2-5 power down control caution micpdb and xauxpdb cannot enter the power up state at the same time (micpdb = xauxpdb = "1"). power up command 0111 10 power down command 0111 00 register address 0001 10 rec2pdb txag txgcr register address 0 0 0 micpdb xauxpdb rec1pdb rauxpdb ringpdb ampcr pre-filter + mixer to v ref to v ref accessory input microphone input + + to v ref micpdb "1" = power on xauxpdb + rauxpdb + rec1pdb accessory output receiver 1 receiver 2 + + ringer output ringpdb stand-by rec2pdb stand-by when both accessory output and receiver 1 amplifiers are in the power down state, these also enter power down state. stand-by d/a stand-by when all input amplifiers are in the power down state, these also enter power down state. digital signal processor stand-by a/d stand-by pll to xacomi 78h 1eh 70h 0eh hex note ml hex note ml note m: hex value with msb first l: hex value with lsb first "1" = power on "1" = power on "1" = power on "1" = ringer output "1" = power on m pd9930 14 register address ampcr d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 micpdb micpdb 0 microphone amplifier power control power down xauxpdb rec1pdb rauxpdb ringpdb 1 power up xauxpdb 0 accessory input amplifier power control power down 1 power up rec1pdb 0 receiver amplifier 1 power control power down 1 power up rauxpdb 0 accessory output amplifier power control power down 1 power up ringpdb 0 ringer output control sets output at low level. 1 output enable (3) input/output amplifier control register (ampcr) this is a 5-bit register for power up/down control of each input/output amplifier (not including receiver amplifier 2), and for ringer output on/off control. remark for information on power up/down control of receiver amplifier 2, refer to 4.1.1 voice send analog gain/ receiver amplifier 2 control register (txgcr) . figure 2-6 input/output amplifier control register remarks 1. in the stand-by mode, all amplifiers enter the power down state regardless of input/output control register settings. however, register contents are held unless reset or written, so when the stand-by mode is cleared by power up command, the command prior to the stand-by mode is resumed. 2. the microphone and accessory amplifiers cannot enter the power up (d4 = d3 = "1") state at the same time. m pd9930 15 table 2-4 function specification by input/output amplifier control register register address ampcr hex note d7 d6 d5 d4 d3 d2 d1 d0 m l 00000000 x x x x stop 00h 00h at reset 00001 x x x x output 01h 80h 00010 x x x o stop 02h 40h 00011 x x x o output 03h c0h 00100 x x o x stop 04h 20h 00101 x x o x output 05h a0h 00110 x x o o stop 06h 60h 00111 x x o o output 07h e0h 01000 x o x x stop 08h 10h 01001 x o x x output 09h 90h 01010 x o x o stop 0ah 50h 01011 x o x o output 0bh d0h 01100 x o o x stop 0ch 30h 01101 x o o x output 0dh b0h 01110 x o o o stop 0eh 70h 01111 x o o o output 0fh f0h 10000 o x x x stop 10h 08h 10001 o x x x output 11h 88h 10010 o x x o stop 12h 48h 10011 o x x o output 13h c8h 10100 o x o x stop 14h 28h 10101 o x o x output 15h a8h 10110 o x o o stop 16h 68h 10111 o x o o output 17h e8h note m: hex value with msb first l: hex value with lsb first remark o: power up x: power down microphone accessory receiver accessory amplifier input amplifier amplifier 1 output amplifier ringer output remarks m pd9930 16 fsync count 238 239 1 0 2 3 240 241 0 0 anapwd clkpwd dsppwd power down command power up command (4) power up/down command (pupcmd/pdwcmd) the stand-by mode is set and cleared by the following two special commands. when resetting, the stand-by mode is set. figure 2-7 power down command (sets to stand-by mode) d7 d6 d5 d4 d3 d2 d1 d0 pdwcmd 011100xx remark x: don't care figure 2-8 power up command (clears stand-by mode) d7 d6 d5 d4 d3 d2 d1 d0 pupcmd 011110xx remark x: don't care power up/down timing remarks count: internal counter (counts with an 8-khz internal clock) anapwd: analog power down (power down when high) clkpwd: clock power down (power down when high) dsppwd: signal processing power down (power down when high) m pd9930 17 power up command execution analog and pll operation start pll clock stabilization clock operation start digital signal operation start power down command execution digital signal processing (filter operation, tone generation operation) operation stop clock (internal clock, serial clock) power down analog (pll, all amplifiers) power down (5) power up/down sequence (a) power down sequence (b) power up sequence remarks 1. the dsp interface serial input/output operation does not stop or start when switching to power up/down. 2. rising time from standby mode to normal operation mode is about 30.5 ms after execution of the power up command. 3. fsync can be stopped at power down. however, input of the fsync clock is necessary during operation and in the above sequence. m pd9930 18 d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 mclk mdat mstr microcontroller pd9930 microcontroller i/f mdat mclk mstr serial i/o sck so port m 2.1.7 microcontroller interface the m pd9930 can control internal functions by microcontroller command. a clock synchronous serial i/o is incorporated to receive command. a clocked serial interface is provided to receive microcontroller commands. a microcontroller connection example is shown in figure 2-9 . 8-bit length data is received by the serial clock (mclk), serial input (mdat), and strobe input (mstr) lines note . the timing chart is shown in figure 2-10 . by reading data to the internal shift register and setting mstr to high level at the mclk rising point, it is latched to the internal control register. data transfer must be made with lsb first. note when 8 bits or more (9 mclk clocks or more) data is input, the last 8-bit which is input immediately before the active edge of mstr is recognized as a control command. figure 2-9 example of connection with microcontroller figure 2-10 microcontroller interface timing chart m pd9930 19 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 si input coding data (15 bits) si g n bit d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 so output coding data (13 bits) si g n bit invalid data 2.1.8 dsp interface a clock synchronous serial i/o is built-in to exchange voice send/receive coding data with an external dsp. 16-bit data is transferred at 8 khz by the serial clock (sclk = 256 khz), serial input (si), serial output (so), and enable output (sen) lines. the reqb is a terminal for allowing/inhibiting data transmission. there are two modes for data input and output timing, and either can be selected by the dspsel terminal. select the mode matching the dsp serial interface input/output timing. data format is as follows: both so output and si input are in 2's complement format with msb first. figure 2-11 data format in dsp interface remark a full code is output when the so pin is +3.17 dbm0 (a/d 1.2 v p-p ). remark when a full code is input to the si pin, the accessory output is 1.2 v p-p . table 2-5 dsp input/output timing mode selection pin input dspsel h mode1 l mode2 table 2-6 allowing data transmission reqb pin input data transmission l data transmission is allowed. enable signal (sen) is output at rising edge of fsync (8 khz), and data input/output is started. h enable signal is not output and data are not input or output. mode m pd9930 20 dsp pd9930 serial i/o sck enable si so port dsp i/f sclk sen so si reqb dspsel note fsync 8 khz m v dd figure 2-12 example of connection with dsp (mode 1) note when using with mode 2, connect dspsel to gnd. m pd9930 21 reqb fsync (8 khz) sen sclk (256 khz) so si 125 s d15 d14 d2 d1 d0 d15 d14 d15 d14 d2 d1 d0 d15 d14 d13 d13 m d13 d12 don't care don't care reqb fsync (8 khz) sen sclk (256 khz) so si 125 s d15 d14 d2 d1 d0 d15 d14 d15 d14 d2 d1 d0 d15 d14 m don't care d13 d13 don't care figure 2-13 dsp interface timing chart (a) mode 1 (dspsel = v dd ) (b) mode 2 (dspsel = gnd) m pd9930 22 2.1.9 dai (digital audio interface) has a on-chip circuit enabling dai functions specified in gsm11.10. the receive system has a on-chip lpf only. if a bpf is necessary, it should be mounted externally. system configuration at the time of dai test mode is shown in figure 2-15 . the dai terminal is connected to the system simulator via the pin 25 dsub socket. the test mode can be selected by terminals tc1 or tc2, or by microcontroller command. dai mode should be set after completing power-up operation (30.5 ms after executing power-up command). when changing the modes from dai to normal, either of the following operations should be executed. ? after specifying normal mode, input the dai reset signal (drstb = low). ? input reset signal (resetb = low). when specifying by command, test control register mode specification bits (itc1, itc2) are used (refer to 4.4.1 test control register (tstcr) .). timing for each mode is shown in figures 2-16 through 2-20 . for operation at the time of each mode, refer to figure 4-13 test mode operation . table 2-7 dai test mode specification tc2 tc1 test mode function (itc2) (itc1) specification 0 0 normal operation note normal operation. this mode is set at system reset (when resetb = low) regardless of status of tc1 and tc2. 0 1 speech encoder outputs data input from di pin to dsp (speech encoder) from so pin. test mode input is started at rising edge of first fsync (8-khz external clock input) after execution of mode specification, and outputting data to dsp is started at next rising edge of fsync. 1 0 speech decoder outputs speech decoder output data input from si pin from do pin. test mode inputting data from dsp is started at rising edge of first fsync (8-khz external clock input) after execution of mode specification, and data is output from do pin at next rising edge of fsync. 1 1 acoustic device, a/d, outputs audio data converted into digital signal from do pin. d/a test mode also inputs audio data input from di pin to d/a converter. inputting/outputting data is started at rising edge of first fsync (8-khz external clock input) after execution of mode specification. at this time, clock output to dsp (sclk) is stopped. note in the normal mode, do not set drstb to low level (during low period, serial interface with dsp is disabled). as well, set the output pins of driver ic to high-impedance state, because drstb input pin is connected with a pull-up resistor. remark analog loop back mode and dai test mode cannot be specified at the same time. dai test mode is set with tc1, tc2 (or itc1, itc2) and drstb pins. dai test mode is entered at the rising edge of the drstb signal when both tc1 and tc2 pins (or itc1 and itc2 pins) are set as shown in figure 2-14 . m pd9930 23 dai dai dclk do di tc1 tc2 drstb fsync mclk mstr mdat sclk sen so si reqb 8 khz dsp (sp-codec) microcontroller test command 25-pin dsub socket system simulator mobile equipment pd9930 m tc1 (itc1) tc2 (itc2) drstb figure 2-14 latch timing of tc1, tc2 (or itc1, itc2) figure 2-15 example of system configuration at time of dai test mode remark in the acoustic device test mode, reqb is ignored (both high and low levels). when dspsel = v dd (mode 1), sclk and sen are fixed to low, and when dspsel = gnd (mode 2), fixed to high. m pd9930 24 tc1 (itc1) "l" drstb reqb fsync (8 khz) dclk (104 khz) di sclk (256 khz) sen so don't care d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d12 d11 d10 d9 d8 d7 d6 d5 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 tc2 (itc2) figure 2-16 speech encoder test mode (dsp interface = mode 1) (tc1 = 1, tc2 = 0) m pd9930 25 tc1 (itc1) tc2 (itc2) drstb reqb fsync (8 khz) dclk (104 khz) di sclk (256 khz) sen so don't care d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d12 d11 d10 d9 d8 d7 d6 d5 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 "l" figure 2-17 speech encoder test mode (dsp interface = mode 2) (tc1 = 1, tc2 = 0) m pd9930 26 tc1 (itc1) tc2 (itc2) drstb reqb fsync (8 khz) sclk (256 khz) sen si dclk (104 khz) do d12 d11 d10 d9 d8 d7 d6 d5 d0 d1 d2 d15 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d0 d1 d2 d15 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 "l" figure 2-18 speech decoder test mode (dsp interface = mode 1) (tc1 = 0, tc2 = 1) m pd9930 27 tc1 (itc1) tc2 (itc2) drstb reqb fsync (8 khz) sclk (256 khz) sen si dclk (104 khz) do d12 d11 d10 d9 d8 d7 d6 d5 d0 d1 d2 d15 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d0 d1 d2 d15 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 "l" figure 2-19 speech decoder test mode (dsp interface = mode 2) (tc1 = 0, tc2 = 1) m pd9930 28 tc1 (itc1) tc2 (itc2) drstb reqb fsync (8 khz) sclk (256 khz) di dclk (104 khz) do d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d12 d11 d10 d9 d8 d7 d6 d5 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d12 d11 d10 d9 d8 d7 d6 d5 note note in dsp interface = mode 2, sclk is fixed to high. figure 2-20 acoustic device test mode (dsp interface = mode 1) (tc1 = 1, tc2 = 1) m pd9930 29 tone generation tone generation (31.25 ms) tone stop (31.25 ms) tone generation (200 ms) tone generation (1 s) tone stop (1 s) (1) continuous tone (2) intermittent tone (when 31.25 ms on/off) (3) one-shot tone (200 ms one-shot) (4) gsm triple tone 3. tone interval output function (timer terminal) when a tone is generated, an interval signal that indicates the tone intermittent state is output. the function is used, for example, to make the led blink in synchronization with the ringer tone. figure 3-1 tone interval output waveform m pd9930 30 4. internal control functions the m pd9930 can control internal functions by commands from a microcontroller. commands consist of 8- bit data (d7 to d0) consisting of register address and setting data, and are written in the following internal registers. register name control (1) voice send analog gain/receiver amplifier 2 control register (txgcr) voice send/receive gain control (2) voice receive analog gain control register (rxgcr) (3) voice send/receive digital gain control register (dggsr) (4) digital signal processing control register (dspcr) digital input/output control (5) tone frequency selection register (frqsr) tone control (6) expanded tone register (expr1/expr2) (7) tone control register (toncr) (8) tone gain control register (tngcr) (9) input/output amplifier control register (ampcr) power up/down control (10) power up control command (pupcmd) (11) power down control command (pdwcmd) (12) test control register (tstcr) test mode control remarks 1. in the case of registers (1), (2), and (9) to (11), written contents are executed instantly. 2. for registers (3) to (8) and (12), since fetch execution is made by the internal clock (125 m s interval), keep 125 m s or more interval for write-in to the same register. if the write-in to the same register is executed continuously, the previous command may be ignored. 3. even when in the stand-by mode, write-in to each internal register is possible (can be held), but the command written in the register is executed only after clearing the stand-by mode. 4.1 send/receive gain control an outline of send/receive gain control is shown in figure 4-1 . with the m pd9930, the following send and receive gain control is possible. send/receive gain control register used voice send gain pre-filter analog gain adjustment voice send analog gain/receiver amplifier 2 control (0, C3 db) control register (txgcr) digital gain fine adjustment voice send/receive digital gain control register (0 to C2.8 db, 0.4 db steps) (dggsr) voice receive gain receiver amplifier 1 analog gain adjustment voice receive analog gain control register control (volume control) (0 to C31 db, 1 db steps) (rxgcr) digital gain fine adjustment voice send/receive digital gain control register (0 to C2.4 db, 0.8 db steps) (dggsr) m pd9930 31 register address 00011 0 rec2pdb txag txgcr pre-filter/mixer voice send analog gain control microphone input or accessory input a/d voice send digital gain control digital signal-processor bpf 0 to ?.8 db (0.4 db steps) so register address 010 dggsr rxdg1 rxdg0 txdg2 txdg1 txdg0 receiver amplifier 1 voice receive analog gain control receiver output d/a voice receive digital gain control si 0 to ?1 db (1 db steps) lpf 0 to ?.4 db (0.8 db steps) 0, ? db register address 001 rxgcr rxag4 rxag3 rxag2 rxag1 rxag0 figure 4-1 send/receive gain control m pd9930 32 register address txgcr d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 1 1 0 rec2pdb txag rec2pdb 0 1 receiver amplifier 2 power up/down specification power down power up txag 0 1 pre-filter analog gain specification sets to 0 db sets to ? db 4.1.1 voice send analog gain/receiver amplifier 2 control register (txgcr) this register controls pre-filter gain. it also controls receiver amplifier 2 power up/down as shown in table 4-1 (refer to 2.1.6 power up/down control ). when power is down, the contents of the register area retained. after power is up, control continues as before power was down. figure 4-2 voice send analog gain/receiver amplifier 2 control register table 4-1 function specification by send analog gain/receiver amplifier 2 control register register address txgcr hex note d7 d6 d5 d4 d3 d2 d1 d0 m l 00011000 power down 0 db 18h 18h at reset 0 0 1 power down C3 db 19h 98h 0 1 0 power up 0 db 1ah 58h 0 1 1 power up C3 db 1bh d8h note m: hex value with msb first l: hex value with lsb first receiver amplifier 2 voice send analog gain remarks m pd9930 33 register address rxgcr d7 d6 d5 d4 d3 d2 d1 d0 0 0 1 rxag4 rxag3 rxag2 rxag1 rxag0 rxag4 to rxag0 00000 to 11111 receiver amplifier 1 gain specification 0 to ?1 db (1 db steps) 4.1.2 voice receive analog gain control register (rxgcr) this is a 5-bit register for controlling the analog gain (volume) of receiver amplifier 1. figure 4-3 voice receive analog gain control register m pd9930 34 table 4-2 function specifications by voice receive analog gain control register register address rxgcr hex note d7 d6 d5 d4 d3 d2 d1 d0 m l 00100000 0 db 20h04h 00001 C1 db 21h84h 00010 C2 db 22h44h 00011 C3 db 23hc4h 00100 C4 db 24h24h 00101 C5 db 25ha4h 00110 C6 db 26h64h 00111 C7 db 27he4h 01000 C8 db 28h14h 01001 C9 db 29h94h 01010 C10 db 2ah 54h 01011 C11 db 2bh d4h 01100 C12 db 2ch 34h 01101 C13 db 2dh b4h 01110 C14 db 2eh 74h 01111 C15 db 2fh f4h 10000 C16 db 30h 0ch 10001 C17 db 31h 8ch 10010 C18 db 32h 4ch 10011 C19 db 33h cch 10100 C20 db 34h 2ch 10101 C21 db 35h ach 10110 C22 db 36h 6ch 10111 C23 db 37h ech 11000 C24 db 38h 1ch 11001 C25 db 39h 9ch 11010 C26 db 3ah 5ch 11011 C27 db 3bh dch 11100 C28 db 3ch 3ch 11101 C29 db 3dh bch 11110 C30 db 3eh 7ch 11111 C31 db 3fh fch at reset note m: hex value with msb first l: hex value with lsb first voice receive analog gain remarks m pd9930 35 register address dggsr d7 d6 d5 d4 d3 d2 d1 d0 010 rxdg1 rxdg0 txdg2 txdg1 txdg0 rxdg1 to rxdg0 00 to 11 receive digital gain specification 0 to ?.4 db (0.8 db steps) txdg2 to txdg0 000 to 111 send digital gain specification 0 to ?.8 db (0.4 db steps) 4.1.3 voice send/receive digital gain control register (dggsr) this is a 5-bit register for adjusting the gain of the digital signal processor. the gain of the send system and receive system can be fine-adjusted independently. figure 4-4 send/receive digital gain control register m pd9930 36 table 4-3 function specifications by voice send/receive digital gain control register register address dggsr hex note d7 d6 d5 d4 d3 d2 d1 d0 m l 01000000 0 db 0 db 40h02hat reset 00001 0 db C0.4 db 41h 82h 00010 0 db C0.8 db 42h 42h 00011 0 db C1.2 db 43h c2h 00100 0 db C1.6 db 44h 22h 00101 0 db C2.0 db 45h a2h 00110 0 db C2.4 db 46h 62h 00111 0 db C2.8 db 47h e2h 01000 C0.8 db 0 db 48h 12h 01001 C0.8 db C0.4 db 49h 92h 01010 C0.8 db C0.8 db 4ah 52h 01011 C0.8 db C1.2 db 4bh d2h 01100 C0.8 db C1.6 db 4ch 32h 01101 C0.8 db C2.0 db 4dh b2h 01110 C0.8 db C2.4 db 4eh 72h 01111 C0.8 db C2.8 db 4fh f2h 10000 C1.6 db 0 db 50h 0ah 10001 C1.6 db C0.4 db 51h 8ah 10010 C1.6 db C0.8 db 52h 4ah 10011 C1.6 db C1.2 db 53h cah 10100 C1.6 db C1.6 db 54h 2ah 10101 C1.6 db C2.0 db 55h aah 10110 C1.6 db C2.4 db 56h 6ah 10111 C1.6 db C2.8 db 57h eah 11000 C2.4 db 0 db 58h 1ah 11001 C2.4 db C0.4 db 59h 9ah 11010 C2.4 db C0.8 db 5ah 5ah 11011 C2.4 db C1.2 db 5bh dah 11100 C2.4 db C1.6 db 5ch 3ah 11101 C2.4 db C2.0 db 5dh bah 11110 C2.4 db C2.4 db 5eh 7ah 11111 C2.4 db C2.8 db 5fh fah note m: hex value with msb first l: hex value with lsb first voice receive voice send digital gain digital gain remarks m pd9930 37 register address 0110 txact tnact soact siact dspcr txact 1 = on note tnact 1 = on digital signal processor bpf lpf tone generator dsp i/f soact 1 0 dgnd dgnd siact 0 1 so si a/d d/a 4.2 digital input/output control an outline of digital input/output control is shown in figure 4-5 . the m pd9930 can control input and output of the digital signal processor as follows. digital input/output control registers used voice send data bpf operation processing execution/stop connection and disconnection to tone output voice send/ digital signal processing control register receive system (dspcr) serial output terminal (so) control serial input terminal (si) control caution you must not connect nor disconnect tone output voice send/receive system in the tone operation. it causes malfunction. figure 4-5 digital input/output control note connected when txact = 0 and tnact = 1. m pd9930 38 register address dspcr d7 d6 d5 d4 d3 d2 d1 0 1 1 0 txact tnact soact siact txact 0 voice send data processing control stops voice send data digital bpf processing. 1 executes voice send data digital bpf processing. tnact 0 tone output control disconnects tone output from voice send/receive systems. 1 connects tone output to voice send/receive systems. soact 0 dsp interface output control sets serial output (so) at low level note . 1 outputs send data (or tone data) to the serial output (so). siact 0 dsp interface input control sets serial input (si) at low level note . 1 inputs receive data to serial input (si). d0 4.2.1 digital signal processing control register (dspcr) this is a 4-bit register for controlling digital signal processor input/output. figure 4-6 digital signal processing control register note test control register can set serial input/output terminal at low level, too (refer to 4.4.1 test control register (tstcr) ). caution before specification of soact bit, be sure to write "0" for siooff bit of test control register. if "0" isn't written for siooff bit, serial output terminal is set at low level, regardless of soact bit. m pd9930 39 table 4-4 function specification by digital signal processing control register register address dspcr hex note d7 d6 d5 d4 d3 d2 d1 d0 m l 01100000 note 2 note 3 60h 06h at reset 0001 note 2 voice receive signal output 61h 86h 0010 inhibiting command 0011 inhibiting command 0100 note 2 tone output 64h 26h 0101 note 2 voice receive signal + tone outpu t 65h a6h 0110 tone output tone output 66h 66h 0111 tone output voice receive signal + tone output 67h e6h 1000 inhibiting command 1001 inhibiting command 1010 voice send signal output note 3 6ah 56h 1011 voice send signal output voice receive signal output 6bh d6h 1100 inhibiting command 1101 inhibiting command 1110 voice send signal output tone output 6eh 76h 1111 voice send signal output voice receive signal + tone output 6fh f6h notes 1. m: hex value with msb first l: hex value with lsb first 2. stops voice send data processing and serial output. 3. stops voice receive data serial input and tone output. serial output control control of output to d/a remarks m pd9930 40 4.3 tone control an outline diagram of the tone generator is shown in figure 4-7 . tone generation is by the tone 1 oscillation circuit and the tone 2 oscillation circuit. the tone 1 oscillation circuit generates high group frequency for dtmf and four types of single tones (tone 1 frequency). the tone 2 oscillation circuit generates low group frequency (tone 2 frequency) for dtmf. dual tone is output by adding tone 1 frequency. in addition to registered tones, other frequencies can be registered. also, gsm triple tone can be generated by special command. examples of tone generation are shown in figure 4-8 . tone control items are shown below. tone control registers used tone frequency registered tone specification of dtmf tone frequency selection register single tone: 400 hz, 425 hz, 2 khz, 2.6 khz (frqsr) selection of gsm triple tone tone control register (toncr) user registration registration of desired tone in 0.3 to 3.4 khz tone frequency selection register tone range. (frqsr) (single tone, dual tone) expanded tone register 1 (expr1) expanded tone register 2 (expr2) generation pattern registered 31.25 ms intermittence, 200 ms intermittence, tone control register pattern 250 ms intermittence, 500 ms intermittence, (toncr) 1s intermittence, 200 ms one-shot tone desired pattern interrupted at desired interval by start/stop command gain control of tone output gain tone gain control register 0 to C30 db (1 db steps), C38.5 db (tngcr) m pd9930 41 register address frqsr 100 frqsel4 frqsel3 frqsel2 frqsel1 frqsel0 register address tngcr 111 tngain4 tngain3 tngain2 tngain1 tngain0 tone 1 oscillation circuit tone 1 frequency 1209 hz 400 hz 1336 hz 425 hz 1477 hz 2000 hz 1633 hz 2600 hz expanded tone register 1 expanded tone 1 frequency start/ stop tone 2 oscillation circuit tone 2 frequency 697 hz 770 hz 852 hz 941 hz expanded tone register 2 expanded tone 2 frequency 3.1 dbm0 ? db ? db 0 1 tone interval generation 0 to ?0 db (1-db steps) ?8.5 db tnact note lpf output (receive signal) ringer output to d/a serial output timer output note digital signal processing control register bit 2 (refer to figure 4-6 ). register address toncr 0 1 1 tnmode tnp2 tnp1 tnp0 start/ stop 3.1 dbm0 (only sign code) ? db figure 4-7 tone control m pd9930 42 gsm triple tone generation set tone gain. tone gain control register select single tone select gsm triple tone start/stop = "1" (start) tone control register end user register tone generation set tone gain. tone gein control register specify "user register" tone frequency selection register "100110" (registration command) + registration data (lower order 2 bits) setting expanded tone register 1 end select single tone. select 200 ms intermittent pattern. start/stop = "1" (start) tone control register registration data (higher-order 8 bits) setting expanded tone register 1 busy tone generation set tone gain. tone gain control register set frequency to 400 hz. tone frequency selection register select single tone select 500 ms intermittent pattern. start/stop = "1" (start) tone control register end dtmf "7" generation set tone gain. tone gain control register set frequency to dtmf "7". tone frequency selection register select dual tone. select continuous tone. start/stop = "1" (start) tone control register end figure 4-8 tone generation examples (a) when generating a busy tone (b) when generating dtmf "7" with continuous tone (400 hz single tone, 500 ms intermittence) (c) when generating gsm triple tone (d) when generating 200 ms intermittent user regis- ter tone (480 hz single tone; coefficient = 0111011100b) m pd9930 43 register address frqsr d7 d6 d5 d4 d3 d2 d1 d0 1 0 0 frqsel4 frqsel4 to frqsel0 00000 to 10100 tone frequency selection refer to table 4-5 function specification by tone frequency selection register . frqsel3 frqsel2 frqsel1 frqsel0 4.3.1 tone frequency selection register (frqsr) this is a 5-bit register for specifying tone 1 (high group frequency for dtmf and four types of single tones) and tone 2 (low group frequency for dtmf) frequency combinations. figure 4-9 tone frequency selection register write operation in this register is instantaneously executed and retained when a command is received, but change of tone generation or generating tone is executed only when "1" is written for start/stop control bit of the tone control register (refer to figure 4-11 tone control register ). when a user registration tone is selected, the tone specified by the expanded tone register (refer to figure 4-10 expanded tone frequency registration procedure ) is generated. caution do not input a command that sets a tone oscillation frequency after inputting a tone oscillation command (writing "1" to the start/stop control bit of the tone control register). m pd9930 44 table 4-5 function specification by tone frequency selection register register address frqsr hex note 1 d7 d6 d5 d4 d3 d2 d1 d0 m l 10000000 dtmf 1 1209 hz 697 hz 80h 01h 00001 dtmf 2 1336 hz 697 hz 81h 81h 00010 dtmf 3 1477 hz 697 hz 82h 41h 00011 dtmf a 1633 hz 697 hz 83h c1h 00100 dtmf 4 1209 hz 770 hz 84h 21h 00101 dtmf 5 1336 hz 770 hz 85h a1h 00110 dtmf 6 1477 hz 770 hz 86h 61h 00111 dtmf b 1633 hz 770 hz 87h e1h 01000 dtmf 7 1209 hz 852 hz 88h 11h 01001 dtmf 8 1336 hz 852 hz 89h 91h 01010 dtmf 9 1477 hz 852 hz 8ah 51h 01011 dtmf c 1633 hz 852 hz 8bh d1h 01100 dtmf * 1209 hz 941 hz 8ch 31h 01101 dtmf 0 1336 hz 941 hz 8dh b1h 01110 dtmf # 1477 hz 941 hz 8eh 71h 01111 dtmf d 1633 hz 941 hz 8fh f1h 10000 400 hz note 2 indefinite value 90h 09h 10001 425 hz note 2 indefinite value 91h 89h 10010 2 khz note 2 indefinite value 92h 49h 10011 2.6 khz note 2 indefinite value 93h c9h at reset 10100 user registration user registration 94h 29h 10101 inhibiting command 10110 inhibiting command 10111 inhibiting command notes 1. m: hex value with msb first l: hex value with lsb first 2. this is single tone. when specifying this tone, be sure to specify the tone control register in the single tone mode (refer to figure 4-11 tone control register ). remark for dtmf tone generation, specify the tone control register in the dual tone mode (refer to figure 4-11 tone control register ). if the register is specified in the single tone mode, only the high group tone (tone 1 frequency) is generated. dtmf function tone 1 frequency tone 2 frequency remarks m pd9930 45 4.3.2 expanded tone registers (expr1, expr2) (1) expanded tone frequency registration procedure the m pd9930 can register desired tone frequencies (expanded tone frequencies) in 0.3 to 3.4 khz range. expanded tone register 1 (expr1) is for registering expanded tone 1 frequency (high group frequency for dtmf and single tone). expanded tone register 2 (expr2) is for registering expanded tone 2 frequency (low frequency for dtmf). the frequency must be specified by 10-bit coefficient (2's complement). registration of single tone is done with expr1 (single-tone generation is impossible by expr2) (refer to figure 4-10 (a) ). when registering dual tone, set high group in expr1 and low group in expr2. write operation in this register can be executed by continuously writing the expanded tone registration command and expanded tone data command (refer to figure 4-10 ). once registered, the frequency is valid until reset or updated. figure 4-10 expanded tone frequency registration procedure (a) expanded tone 1 frequency registration procedure <1> set expanded tone 1 registration command in expr1. expanded tone 1 registration command d7 d6 d5 d4 d3 d2 d1 d0 expr1 100110ea1ea0 <2> set higher-order 8 bits of expanded tone coefficient (expanded tone 1 data command) in expr1. expanded tone 1 data command d7 d6 d5 d4 d3 d2 d1 d0 expr1 ea9 ea8 ea7 ea6 ea5 ea4 ea3 ea2 remark ea9 to ea0: tone 1 frequency 10-bit coefficient (b) expanded tone 2 frequency registration procedure <1> set expanded tone 2 registration command in expr2. expanded tone 2 registration command d7 d6 d5 d4 d3 d2 d1 d0 expr2 100111eb1eb0 <2> set higher-order 8 bits of expanded tone coefficient (expanded tone 2 data command) in expr2. expanded tone 2 data command d7 d6 d5 d4 d3 d2 d1 d0 expr2 eb9 eb8 eb7 eb6 eb5 eb4 eb3 eb2 remark eb9 to eb0: tone 2 frequency 10-bit coefficient caution after executing the expanded tone registration command, the next command is written as expanded tone data, so continuously execute the expanded tone data command. m pd9930 46 (2) expanded tone data determination method the coefficient e of the tone frequency fe (0.3 to 3.4 khz) to be generated is determined by the following formula. e = cos (2 p fe/fs) fs = 8 khz coefficient e: sign bit 1 bit + 9 bits below the decimal point (coefficient: 2's complement) example when specifying 400 hz single tone cos (2 p x 400/8000) = cos ( p x 0.1) = cos (0.3141592653......) = 0.951056516...... = (0.11110011x) b (higher-order 9 bits are determined.) next, the least significant bit is determined. when (0.11110011 0) b = 0.94921875 2 p fe' x fs = cos C1 (0.94921875) = 0.320052983 fe' = 0.320052983 x fs/(2 p ) fe' = 407.504115 when (0.11110011 1) b = 0.951071875 2 p fe" x fs = cos C1 (0.951071875) = 0.314109559 fe" = 0.314109559 x fs/(2 p ) fe" = 399.524415 since fe" is nearest to 400 hz, the coefficient to be registered is (0.111100111) b = (1e7) h. 0111100111 ea9 ea8 ea7 ea6 ea5 ea4 ea3 ea2 ea1 ea0 the error of oscillation frequency by rounding 10-bit coefficient is below 5 hz (max. at 300 hz ? 1.7 %) for all frequencies. about 1.67 % near 300 hz ( 5 hz) about 1.00 % near 500 hz ( 5 hz) about 0.40 % near 1 khz ( 5 hz) about 0.25 % near 2 khz ( 5 hz) about 0.16 % near 3 khz ( 5 hz) coefficient is negative number in fe > 2.0 khz. m pd9930 47 register address toncr d7 d6 d5 d4 d3 d2 d1 d0 1 0 1 tnmode tnmode 0 single tone/dual tone specification single tone mode tnp2 tnp1 tnp0 start /stop 1 remarks dual tone mode at reset tnp2 0 generation pattern selection continuous tone generation 0 31.25 ms tone, 31.25 ms no tone repeated at reset 0 0 1 1 1 1 tnp1 0 0 1 1 0 0 1 1 tnp0 0 1 0 1 0 1 0 1 200 ms tone, 200 ms no tone repeated 250 ms tone, 250 ms no tone repeated 500 ms tone, 500 ms no tone repeated 1 s tone, 1s no tone repeated gsm triple tone generated note 1 200 ms interval tone generated (one shot tone) start/stop 0 tone generation/stop control stop ("1" ? "0", "0" ? "0" both valid) 1 remarks validation of tone ferquency selection register setting data, start of generation ("1" ? "1", "0" ? "1" both valid) at reset remarks note 2 4.3.3 tone control register (toncr) this is a 5-bit register for controlling single tone/dual tone specification, generation pattern selection, and generation and stopping. figure 4-11 tone control register notes 1. 950 hz tone 333 ms, 1400 hz tone 333 ms, 1800 hz tone 333 ms, 1 s no tone repeated. 2. do not input a command that sets a tone oscillation frequency after inputting a tone oscillation command (writing "1" to the start/stop control bit of the tone control register). remark when the regeneration pattern is specified as "110", it becomes gsm triple tone command, so tone generation forcibly enters single tone mode. tone generation and change of a tone that is being generated is executed only when "1" is written for start/ stop control bit (d0 bit) (refer to figure 4-11 and table 4-6 ). m pd9930 48 register address tngcr d7 d6 d5 d4 d3 d2 d1 d0 1 1 1 tngain4 tngain3 tngain2 tngain1 tngain0 tngain4 to tngain0 00000 to 11111 tone gain selection (refer to table 4-7 function specification by tone gain control register ). 0 to ?0 db (1 db steps), ?8.5 db table 4-6 function specification by tone control register register address toncr hex note d7 d6 d5 d4 d3 d2 d1 d0 ml 10 1xxxx0 tone stop a0h 05h 00001 continuous single tone generation a1h 85h 00011 31.25 ms intermittent single tone generation a3h c5h 00101 200 ms intermittent single tone generation a5h a5h 00111 250 ms intermittent single tone generation a7h e5h 01001 500 ms intermittent single tone generation a9h 95h 010111 s intermittent single tone generation abh d5h 01101 gsm triple tone generation adh b5h 01111 200 ms one-shot single tone generation afh f5h 10001 continuous dual tone generation b1h 8dh 10011 31.25 ms intermittent dual tone generation b3h cdh 10101 200 ms intermittent dual tone generation b5h adh 10111 250 ms intermittent dual tone generation b7h edh 11001 500 ms intermittent dual tone generation b9h 9dh 110111 s intermittent dual tone generation bdh bdh 11111 200 ms one-shot dual tone generation bfh fdh note m: hex value with msb first l: hex value with lsb first remark x: don't care 4.3.4 tone gain control register (tngcr) this is a 5-bit register for controlling the tone output gain. figure 4-12 tone gain control register tone control conditions m pd9930 49 table 4-7 function specification by tone gain control register register address tngcr hex note d7 d6 d5 d4 d3 d2 d1 d0 m l 11100000 0 db e0h07h 00001 C1 db e1h87h 00010 C2 db e2h47h 00011 C3 db e3hc7h 00100 C4 db e4h27h 00101 C5 db e5ha7h 00110 C6 db e6h67h 00111 C7 db e7he7h 01000 C8 db e8h17h 01001 C9 db e9h97h 01010 C10 db eah 57h 01011 C11 db ebh d7h 01100 C12 db ech 37h 01101 C13 db edh b7h 01110 C14 db eeh 77h 01111 C15 db efh f7h 10000 C16 db f0h 0fh 10001 C17 db f1h 8fh 10010 C18 db f2h 4fh 10011 C19 db f3h cfh 10100 C20 db f4h 2fh at reset 10101 C21 db f5h afh 10110 C22 db f6h 6fh 10111 C23 db f7h efh 11000 C24 db f8h 1fh 11001 C25 db f9h 9fh 11010 C26 db fah 5fh 11011 C27 db fbh dfh 11100 C28 db fch 3fh 11101 C29 db fdh bfh 11110 C30 db feh 7fh 11111 C38.5 db ffh ffh note m: hex value with msb first l: hex value with lsb first tone gain remarks m pd9930 50 4.4 test mode control the m pd9930 has the following test functions. test function registers used dai test function this test function is stipulated in gsm11.10. test mode selection can be test control controlled by external terminal (tc1 or tc2) or internal register (itc1, register (tstcr) itc2). analog loopback function send data after bpf processing is input to lpf. dsp interface input/ so, si, sclk and sen terminals can be set at low level. output control function an outline of test mode control is shown in figure 4-13 . m pd9930 51 mobile station pd9930 m dsp i/f dsp tx so dai speech encoder di tc1 tc2 1 0 system simulator mobile station pd9930 m dsp i/f dsp rx si dai speech decoder do tc1 tc2 1 0 system simulator mobile station pd9930 m a/d d/a bpf lpf dai do di tc1 tc2 1 1 a/d d/a bpf lpf pd9930 m (a) dai (speech encoder test mode) (b) dai (speech decoder test mode) (c) dai (a/d, d/a test mode) (d) analog loopback mode system simulator figure 4-13 test mode operation m pd9930 52 register address tstcr d7 d6 d5 d4 d3 d2 d1 d0 1 1 0 tcmode tcmode 0 dai test mode control method selection specification of test mode by external terminals tc1 and tc2 itc2 itc1 loopbk siooff 1 specification of test mode by test control registers itc1 and itc2 itc2 0 dai test mode specification normal operation 0 speech encoder test mode loopbk 0 analog loopback specification normal operation 1 analog loopback siooff 0 dsp interface input/output terminal control normal operation 1 setting of terminals so, si, sclk, and sen to low level 1 1 itc1 0 1 0 1 remarks at reset remarks at reset speech decoder test mode acoustic device, a/d, d/a test mode remarks at reset remarks at reset 4.4.1 test control register (tstcr) this is a 5-bit control register for selecting the test mode. itc1, itc2 become valid at the rising edge of drstb. for the precautions when using dai, refer to 2.1.9 dai (digital audio interface) . figure 4-14 test control register remark the analog loopback mode and the dai test mode cannot be specified at the same time. m pd9930 53 5. electrical characteristics absolute maximum ratings (t a = 25?c, dgnd = agnd1 to agnd4 = 0 v) item symbol conditions ratings unit supply voltage v dd av dd1 , av dd2 , dv dd C0.3 to +5.5 v analog input voltage v ain all analog input pins C0.3 to v dd +0.3 v digital input voltage v din all digital input pins C0.3 to v dd +0.3 v analog output pin applied voltage v aout all analog output pins C0.3 to v dd +0.3 v digital output pin applied voltage v dout all digital output pins C0.3 to v dd +0.3 v operating ambient temperature t a C30 to +85 ?c storage temperature t stg C65 to +150 ?c cautions 1. connect the agnd1 through agnd4 pins and dgnd pin to an analog ground line near m pd9930 pins. connect the dv dd , av dd1 , av dd2 pins to an analog power supply line near m pd9930 pins. 2. do not connect output (and bidirectional) pins each other. do not connect output (or bidirec- tional) pins directly to the v dd , v cc , or gnd line. however, open drain pin and open collector pin can be directly connected to v dd , v cc , or gnd line. if timing design is made so that no signal conflict occurs, three-state pins can also be connected directly to three-state pins of external circuit. 3. exposure to absolute maximum ratings for extended periods may affect device reliability; exceeding the ratings could cause permanent damage. the parameters apply independently. the device should be operated within the limits specified under dc and ac characteristics. m pd9930 54 recommended operating range (t a = C30 to +85?c) (1) dc condition item symbol conditions min. typ. max. unit supply voltage v dd av dd1 , av dd2 , dv dd 2.7 3.0 3.6 v high level input voltage v ih all digital input pins 0.7 v dd v dd v low level input voltage v il all digital input pins 0 0.3 v dd v analog input voltage v ia all analog input pins 0.6 1.8 v microphone input analog input voltage v mic differential: mici+, miciC 1.2 v p-p gain setting range g mic set with external resistor 15 33 db load resistance rl mic includes gain setting resistance 50 k w load capacitance cl mic 20 pf accessory input analog input voltage v auxi xauxiC 1.2 v p-p gain setting range g auxi set with external resistor 0 10 db load resistance rl auxi includes gain setting resistance 300 k w load capacitance cl auxi 20 pf pre-filter + mixer input analog input voltage v mixi mixi 1.2 v p-p accessory output load resistance rl auxo 100 k w load capacitance cl auxo 100 pf receiver 1 output load resistance rl rec1 100 k w load capacitance cl rec1 20 pf receiver 2 output analog input voltage v rec2 rec2i- 1.2 v p-p gain setting range g rec2 set with external resistor C +10 db load resistance rl rec2 60 nf series 2 k w load capacitance cl rec2 2 k w series 60 nf reference voltage output load capacitance cl acom xacomo, racomo 0.2 10 m f (2) frame signal (fsync) and reset signal (resetb) item symbol conditions min. typ. max. unit fsync frequency fs 7.995 8.000 8.005 khz fsync high level width t whs 2.0 m s fsync low level width t wls 2.0 m s fsync rise time t r 20 ns fsync fall time t f 20 ns resetb low level width t rsl 260 ns m pd9930 55 (3) microcontroller interface item symbol conditions min. typ. max. unit mclk cycle time t mcy 240 ns mclk high level width t mch 100 ns mclk low level width t mcl 100 ns mclk rise time t mr 20 ns mclk fall time t mf 20 ns mdat setup time to t sumda 50 ns mstr - mdat hold time from t hmda 50 ns mclk - mstr high level width t wmst 320 ns mclk setup time to t sumck 0ns mstr - mstr setup time to t sumst 100 ns mclk - (4) dsp interface item symbol conditions min. typ. max. unit si setup time to sclk t susi 200 ns si hold time from sclk t hsi 200 ns (5) dai item symbol conditions min. typ. max. unit di setup time to dclk - t sudi 200 ns di hold time from dclk - t hdi 200 ns tc1, tc2 rise time t tr 50 ns tc1, tc2 fall time t tf 50 ns drstb low level width t drsl 130 m s drstb rise time t drr 20 ns drstb fall time t drf 20 ns dai mode setting time 1 t tcf 60 ms dai mode setting time 2 t tcr 260 m s reqb low level width t drql 130 m s reqb high level width t drqh 130 m s reqb rise time t drqr 20 ns reqb fall time t drqf 20 ns m pd9930 56 capacitance (t a = 25?c) item symbol conditions min. typ. max. unit digital output pin c od f = 1 mhz 20 pf capacitance digital input pin c id f = 1 mhz 20 pf capacitance dc characteristics (t a = 25?c, v dd = 2.7 to 3.6 v (gnd standard)) (1) current consumption item symbol conditions min. typ. max. unit circuit current in normal i dd1 microphone input 7.0 9.0 ma mode (1020 hz: C10 dbm0) accessory input: power down serial input (1020 hz: C10 dbm0) accessory output: power up receiver 1, 2: power up circuit current in dai i dd2 microphone input 7.5 10.0 ma operation (1020 hz: C10 dbm0) accessory input: power down serial input (1020 hz: C10 dbm0) accessory output: power up receiver 1, 2: power up circuit current in standby i dd3 di, drstb, tc1, tc2: open 50 100 m a mode fsync: 8 khz other digital input pins: 0 or v dd (2) digital part item symbol conditions min. typ. max. unit digital input leak current i lh v i = v dd 1.0 m a i ll v i = 0 C1.0 m a pull-up/down current i il v dd = 3.3 v, 0 v i v dd 100 m a low level output voltage v ol i ol = 2.0 ma 0.4 v high level output voltage v oh i oh = C2.0 ma 2.4 v m pd9930 57 (3) analog part item symbol conditions min. typ. max. unit pre-filter + mixer volume range g prf C3 0 db volume accuracy d g prf volume 0 db standard C3.2 C3.0 C2.8 db cross-talk 1 between ct in1 microphone input amplifier: power down C45 db input channels mici = 1.2 v p-p xauxiC = 0 v p-p accessory input gain setting: 0 db cross-talk 2 between ct in2 accessory input amplifier: power down C45 db input channels mici = 0 v p-p xauxiC = 1.2 v p-p accessory input gain setting: 0 db accessory output maximum output v amax 1.2 v p-p voltage receiver 1 output maximum output v r1max 1.2 v p-p voltage volume range g rec1 C31 0 db volume accuracy d g rec1 volume: 0 to C16 db C1.5 C1.0 C0.5 db volume note : C17 to C31 db C2.0 C1.0 0.0 db receiver 2 output maximum output v r2max distortion factor 4 % (max.) 4 v p-p voltage reference voltage output output voltage v acom xacomo, racomo 1.2 v note simple decrease in the gain due to drop of volume is guaranteed. (4) tone generator item symbol conditions min. typ. max. unit output signal level v tn1 tone 1 C2.93 C2.73 dbm0 v tn2 tone 2 C5.93 C5.73 frequency deviation d f tn 0.3 to 3.4 khz C5 +5 hz distortion factor tnsd accessory output 30 db tone volume range g tn C38.5 0 db tone volume accuracy d g tn volume: 0 to C30 db (1 db steps) C1.4 C1.0 C0.8 db m pd9930 58 ac characteristics (1) dsp interface (t a = C30 to +85?c, v dd = 2.7 to 3.6 v, c l = 100 pf) item symbol conditions min. typ. max. unit sclk cycle time t scy 3906 ns sclk high level width t sch 1953 ns sclk low level width t scl 1953 ns sclk rise time t sr 20 ns sclk fall time t sf 20 ns sclk delay time from t dsclk 1.0 m s fsync - sen - delay time from t dsenr 80 ns fsync - sen delay time from t dsenf 80 ns sclk - : mode 1 sen delay time from sclk : mode 2 so output delay time t dso 40 ns from sclk - : mode 1 so output delay time from sclk : mode 2 (2) dai (t a = C30 to +85?c, v dd = 2.7 to 3.6 v, c l = 100 pf) item symbol conditions min. typ. max. unit dclk cycle time t dcy 9615 ns dclk high level width t dch 4808 ns dclk low level width t dcl 4808 ns dclk rise time t dr 20 ns dclk fall time t df 20 ns dclk delay time from t ddclk 200 ns fsync - do output delay time t ddo 200 ns from dclk (3) others (digital output) (t a = C30 to +85?c, v dd = 2.7 to 3.6 v, c l = 100 pf) item symbol conditions min. typ. max. unit timer/ringer rise time t ddr timer pin and ringer pin 50 ns timer/ringer fall time t ddf timer pin and ringer pin 50 ns m pd9930 59 mstr mclk mdat t wmst t sumck t sumst t mch t mcy t sumda t hmda t mr t mcl t mf d0 d1 d2 d6 d7 d0 resetb t rsl frame signal (fsync) remark during normal operation or the power up/down sequence, be sure to input the frame signal. reset signal (resetb) remarks 1. the reset signal is input as it is without shaping, so take full precautions against noise. 2. a power on reset circuit is not incorporated, so be sure to set reset to low after turning the power on. microcontroller interface timing remark d0 to d7: microcontroller command (lsb first) 1/fs t whs t r t wls t f fsync m pd9930 60 sclk fsync sen so si t dsclk t scy t sch t sr t scl t sf t dsenf t dsenr t dso t susi t hsi d15 d14 d13 d1 d0 don't care d15 d14 d13 d0 don't care sclk fsync sen so si t dsclk t scy t scl t sf t sch t sr t dsenr t dsenf t dso t susi t hsi d15 d14 d13 d1 d0 don't care d15 d14 d13 d0 don't care dsp interface timing (mode 1) dsp interface timing (mode 2) m pd9930 61 fsync t ddclk dclk do t dcy t dch t dr t dcl t df d12 d11 d10 d9 d8 d7 t ddo fsync t ddclk dclk di t dcy t dch t dr t sudi t hdi t dcl t df d12 d11 d10 d9 d8 d7 dai input timing remark d12 to d0: input data (msb first) dai output timing remark d12 to d0: output data (msb first) m pd9930 62 tc1, tc2 t tcf drstb t tr , t tf t tcr t tr , t tf t drr t drf t drsl timer, ringer t ddf t ddr reqb t drqh t drqf t drql t drqr tc1, tc2, drstb input timing timer, ringer output timing reqb input timing m pd9930 63 transmission characteristics transmission characteristics are as indicated below unless otherwise specified. ? analog input analog input signal (C10 dbm0, 1020 hz) ? accessory input part accessory input: set gain 0 db microphone input: power down pre-filter + mixer: set gain 0 db ? analog output analog output signal ? accessory output part receiver output: power down ? digital gain set send and receive: 0 db ? digital input signal level: 0 dbm0 ?t a = 25?c, v dd = 2.7 to 3.6 v (gnd standard) (1) send/receive zero transmission level (0 dbm0 level) item symbol conditions min. typ. max. unit send zero transmission v 0tlpx 600 w standard C8.4 dbm level receive zero transmission v 0tlpr 600 w standard C8.4 dbm level (2) gain characteristics item symbol conditions min. typ. max. unit send gain deviation g x C0.5 +0.5 db receive gain deviation g r C0.5 +0.5 db send gain deviation d g x C0.4 +0.4 db temperature power fluctuation receive gain deviation d g r C0.4 +0.4 db temperature power fluctuation (3) transmission loss level item symbol conditions min. typ. max. unit send transmission loss g tx +3 to C40 dbm0 C0.4 +0.4 db C40 to C50 dbm0 C0.6 +0.6 db C50 to C55 dbm0 C1.2 +1.2 db receive transmission loss g tr +3 to C40 dbm0 C0.4 +0.4 db C40 to C50 dbm0 C0.6 +0.6 db C50 to C55 dbm0 C1.2 +1.2 db level level m pd9930 64 acom, gain 0 db, c message filter frequency characteristics frequency characteristics (4) transmission gain frequency characteristics item symbol conditions min. typ. max. unit send transmission gain g rx1 60 hz C23 db g rx2 200 hz C2.5 0 db g rx3 0.3 to 3.0 khz C0.3 +0.3 db g rx4 3.2 khz C0.65 +0.3 db g rx5 3.4 khz C0.8 0 db g rx6 4.0 khz C14 db g rx7 4.6 khz or more C28 db receive transmission gain g rr3 0.3 to 3.0 khz C0.3 +0.3 db g rr4 3.2 khz C0.65 +0.3 db g rr5 3.4 khz C0.8 0 db g rr6 4.0 khz C14 db g rr7 4.6 khz or more C28 db (5) noise characteristics item symbol conditions min. typ. max. unit send noise n xc microphone power down, xauxiC ? 25 dbrnc0 C65 dbm0c receive noise n rc1 c message filter, input +0 code from si 25 dbrnc0 C65 dbm0c single frequency noise n sf send input ? receive output C50 dbm0 cross-talk between send ct tr no sidetone pass, microphone power down C60 db and receive channels input 0 dbm0 and 1020 hz from xauxiC input +0 code from si cross-talk between receive ct rt no sidetone pass, microphone power down C60 db and send channels xauxiC ? acom input 0 dbm0 and 1020 hz from si power supply voltage psrr v dd 100 mv 0-p signal application 30 db variation rejection f = 0 to 3.4 khz m pd9930 65 012345678910111213141516 ?5 ?0 ?5 ?0 ?5 ?0 ?5 ?0 ?5 ?0 ?5 ?0 ?5 ?0 ? 0 5 frequency (khz) send transmission gain (db) (6) distortion factor characteristics item symbol conditions min. typ. max. unit send channel total power sd x 0 to C10 dbm0 35 db C40 dbm0 25 C45 dbm0 20 receive channel total sd r 0 to C10 dbm0 35 db C40 dbm0 25 C45 dbm0 20 absolute delay d a xauxiC ? rauxo 550 m s delay distortion frequency d o xauxiC ? rauxo 500 hz 1.40 ms 600 hz 0.70 1 khz 0.20 2.6 khz 0.20 2.8 khz 1.40 send transmission gain frequency characteristics 1 (g rx ) distortion factor power distortion factor characteristics m pd9930 66 012345678910111213141516 ?5 ?0 ?5 ?0 ?5 ?0 ?5 ?0 ?5 ?0 ?5 ?0 ?5 ?0 ? 0 5 fre q uenc y ( khz ) receive transmission gain (db) 0 ?.9 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 ?.8 ?.7 ?.6 ?.5 ?.4 ?.3 ?.2 ?.1 0 0.1 send transmission gain (db) fre q uenc y ( khz ) send transmission gain frequency characteristics 2 (g rx ) receive transmission gain frequency characteristics 1 (g rr ) m pd9930 67 0 ?.9 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 ?.8 ?.7 ?.6 ?.5 ?.4 ?.3 ?.2 ?.1 0 0.1 receive transmission gain (db) fre q uenc y ( khz ) receive transmission gain frequency characteristics 2 (g rr ) m pd9930 68 send/receive zero transmission level (0 dbm0 level) is explained below for your reference. (a) send zero transmission level analog output signal level at which the digital input signal level of the d/a converter becomes 0 dbm0. (b) receive zero transmission level analog input signal level at which the digital output signal level of the a/d converter becomes 0 dbm0. (c) analog signal level (dbm) the conversion expression of the amplitude voltage of a signal and an analog signal level is as follows: x = 10 logw x: analog signal level (dbm) w: analog signal power (mw) w = (v 2 /r) x 10 3 v: effective value of analog signal (ac) (vrms) r: resistance ( w ) with the m pd9930, the signal voltage (effective value) can be calculated if r = 600 w and x = C8.4 dbm are substituted. w = 0.1445 (mw) v = 0.294 (vrms) to calculate v 0-p , multiply the signal voltage (effective value) by ? 2. v 0-p = 0.416 (v) (d) digital signal level (dbm0) signal level where the level of the full swing of the digital output value of the a/d converter and the digital input value of the d/a converter is considered to be 3.17 dbm0 (the amplitude of the analog signal is 1.2 v p-p where the gain of the microphone input or accessory input is 0 db). m pd9930 69 + v ref 15 to 33 db 0 db or ? db 0 to ?.8 db (0.4 db steps) a/d digital gain control 0 ?0 ?0 ?0 ?0 ?0 ?0 ?3.4 dbm ?1.4 dbm ?0 dbm0 ?5.8 dbm0 [dbm] 0 ?0 ?0 ?0 ?0 ?0 ?0 [dbm0] analog gain control voice send level diagram (microphone input) remarks 1. thick line: indicates case where gain of microphone amplifier is set to 15 db, gain of analog gain control to 0 db, and gain of digital gain control to 0 db. thin line: indicates case where gain of microphone amplifier is set to 33 db, gain of analog gain control to C3 db, and gain of digital gain control to C2.8 db. 2. overload level: 3.17 dbm0. m pd9930 70 0 to ?1 db (1 db steps) 0 to ?.4 db (0.8 db steps) d/a 0 ?0 ?0 ?0 ?0 ?0 ?0 ?8.4 dbm ?1.8 dbm ?0 dbm0 [dbm] 0 ?0 ?0 ?0 ?0 ?0 ?0 [dbm0] analog gain control digital gain control receiver 1 voice receive level diagram (receiver output) remarks 1. thick line: indicates case where gain of analog gain control is set to 0 db and gain of digital gain control to 0 db. thin line: indicates case where gain of analog gain control is set to C31 db and gain of digital gain control to C2.4 db. 2. overload level: 3.17 dbm0. m pd9930 71 + v ref 0 to 10 db 0 db or ? db 0 to ?.8 db (0.4 db steps) a/d 0 ?0 ?0 ?0 ?0 ?0 ?0 ?8.4 dbm ?8.4 dbm ?0 dbm0 ?5.8 dbm0 [dbm] 0 ?0 ?0 ?0 ?0 ?0 ?0 [dbm0] analog gain control digital gain control voice send level diagram (accessory input) remarks 1. thick line: indicates case where gain of microphone amplifier is set to 0 db, gain of analog gain control to 0 db, and gain of digital gain control to 0 db. thin line: indicates case where gain of microphone amplifier is set to 10 db, gain of analog gain control to C3 db, and gain of digital gain control to C2.8 db. 2. overload level: 3.17 dbm0. m pd9930 72 voice receive level diagram (accessory output) remarks 1. thick line: indicates case where gain of digital gain control is set to 0 db. thin line: indicates case where gain of digital gain control is set to C2.4 db. 2. overload level: 3.17 dbm0. 0 db (fix) 0 to ?.4 db (0.8 db steps) d/a accessory output 0 ?0 ?0 ?0 ?0 ?0 ?0 ?8.4 dbm ?0.8 dbm ?0 dbm0 [dbm] 0 ?0 ?0 ?0 ?0 ?0 ?0 digital gain control [dbm0] m pd9930 73 1 f 1 f 12 k w 100 k w to 500 k w 0.1 f 300 k w 100 k w to 300 k w accessory input 2.2 f + 0.1 f 0.1 f + 2.2 f note 100 k w to 900 k w 0.1 f 100 k w to 300 k w 300 k w 0.1 f accessory output + + 4.7 f 4.7 f 0.1 f dsp to reqb micro- controller dsub socket (25 pin) v (mode 1) or gnd (mode 2) dd from dsp from reset circuit 8 khz 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 mixi xauxo xauxi xacomi xacomo racomo racomi rec2o+ rec2o ic rec2i dspsel ringer timer tc2 tc1 dclk do di drstb mclk mdat mstr test sclk so si sen dv dd av dd2 av dd1 rauxo rec1o agnd1 agnd2 agnd3 agnd4 reqb resetb fsync dgnd mici+ mici mico 0.1 f note when connecting a dynamic receiver, use a drive amplifier. pd9930g-22 m m m m m m m m m m mm low-current drive led m m 6. applied circuit example m pd9930 74 44 pin plastic qfp ( 10) b a 33 23 34 22 111 44 12 c d f g h j i m p k l n detail of lead end s 5? 5? q m note each lead centerline is located within 0.15 mm (0.006 inch) of its true position (t.p.) at maximum material condition. p44g-80-22-2 item millimeters inches a b c d f g h i j k l m n p q s 13.6 0.4 0.15 1.65 max. 10.0 0.2 10.0 0.2 13.6 0.4 1.0 1.0 0.2 +0.10 ?.05 1.45 0.1 0.05 0.05 0.15 0.8 (t.p.) 1.0 0.35 0.10 1.8 0.2 0.15 0.039 0.039 0.535 +0.017 ?.016 0.394 +0.008 ?.009 0.394 +0.008 ?.009 0.535 +0.017 ?.016 0.006 0.031 (t.p.) 0.014 +0.004 ?.005 0.071 +0.008 ?.009 0.039 +0.009 ?.008 0.006 +0.004 ?.003 0.006 0.002 0.002 0.065 max. 0.057 +0.005 ?.004 7. package drawings m pd9930 75 8. recommended soldering conditions the following conditions must be met for soldering conditions of the m pd9930. for more details, refer to our document "semiconductor device mounting technology manual" (c10535e). please consult with our sales offices in case other soldering process is used, or in case the soldering is done under different conditions. type of surface mount device m pd9930g-22: 44-pin plastic qfp (10 x 10 mm) soldering process soldering conditions symbol infrared ray reflow peak temperature of package surface: 235?c or below, ir35-107-2 reflow time: 30 seconds or below (210?c or higher), number of reflow processes: max. 2 exposure limit note : 7 days (10 hours pre-baking is required at 125?c afterwards) vps peak temperature of package surface: 215?c or below, vp15-107-2 reflow time: 40 seconds or below (200?c or higher), number of reflow processes: max. 2 exposure limit note : 7 days (10 hours pre-baking is required at 125?c afterwards) wave soldering soldering bath temperature: 260?c or below, ws60-107-1 reflow time: 10 seconds or below, number of reflow processes: 1 preheating temperature: 120?c max. (package surface temperature) exposure limit note : 7 days (10 hours pre-baking is required at 125?c afterwards) partial heating method terminal temperature: 300?c or below, time: 3 seconds or below (per one side of the device). note exposure limit before soldering after dry-pack package is opened. storage conditions: 25?c and relative humidity at 65 % or less. caution do not apply more than one soldering method at any one time, except for "partial heating method". m pd9930 76 [memo] m pd9930 77 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos device behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. produc- tion process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed imme- diately after power-on for devices having reset function. m pd9930 78 [memo] no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. anti-radioactive design is not implemented in this product. m4 96.5 the application circuits and their parameters are for reference only and are not intended for use in actual design-ins. the export of this product from japan is prohibited without governmental license. to export or re-export this product from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative. |
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